PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 182

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

4.7.21 Receive Byte Count High (RBCH)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 000xxxxx
DMA
OV
RBC11..8 Receive Byte Count high.
4.7.22 Transmit Byte Count Low (XBCL)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
XBC7..0
Semiconductor Group
bit 7
bit 7
XBC7
DMA
DMA-mode status indication.
Read back value representing the DMA-bit programmed in register XBCH.
Counter Overflow.
A ’1’ indicates that more than 4095 bytes were received.
The received frame exceeded the byte count in RBC11…RBC0.
Together with RBCL (bits RBC7…RBC0) the length of the received frame
can be determined.
Together with XBCH (bits XBC11…XBC8) this register is used in DMA-
mode to program the length of the next frame to be transmitted (1…4096
bytes). The number of transmitted bytes is XBC + 1.
Consequently the SACCO can request the correct number of DMA-cycles
after a XDD/XTF- or XDD-command.
XBC6
H
0
H
XBC5
0
XBC4
OV
182
RBC11
XBC3
read
read
write
write
address: (Ch-A/Ch-B): 2D
address: (Ch-A/Ch-B): 5A
address: (Ch-A/Ch-B): 2A
address: (Ch-A/Ch-B): 54
Detailed Register Description
RBC10
XBC2
RBC9
XBC1
PEB 20550
PEF 20550
bit 0
bit 0
RBC8
XBC0
H
H
H
H
/D4
/DA
/6A
/6D
01.96
H
H
H
H