PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 155

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

The timer is started as soon as CMDR:ST is set to 1 and stopped by writing the
TIMR-register or by selecting OMDR:OMS0 = 0.
4.6.28 Status Register EPIC
Access in demultiplexed P-interface mode:
The status register STAR displays the current state of certain events within the EPIC-1.
The STAR register bits do not generate interrupts and are not modified by reading
STAR.
MAC
TVAL6..0 Timer Value bits 6..0; the timer period, equal to (1+TVAL6..0)
Access in multiplexed P-interface mode:
Reset value: 05
Note: MAC is also set and reset during synchronous transfers.
TAC
PSS
MFTO
MFAB
MFAE
Semiconductor Group
bit 7
MAC
programmed here. It can thus be adjusted within the range of 250 s up to
32 ms.
Memory Access
0…no memory access is in operation.
1… a memory access is in operation. Hence, the memory access registers
may not be used.
Timer Active
0… the timer is stopped.
1… the timer is running.
PCM-Synchronization Status.
1… the PCM-interface is synchronized.
0… the PCM-interface is not synchronized. There is a mismatch between the
PBNR-value and the applied clock and framing signals (PDC/PFS) or
OMDR:OMS0 = 0.
MF-Channel Transfer in Operation.
0… no MF-channel transfer is in operation.
1… an MF-channel transfer is in operation.
MF-Channel Transfer Aborted.
0… the remote receiver did not abort a handshake message transfer.
1… the remote receiver aborted a handshake message transfer.
MFFIFO-Access Enable.
0… the MFFIFO may not be accessed.
1… the MFFIFO may be either read or written to.
TAC
H
PSS
®
-1 (STAR_E)
MFTO
155
MFAB
read
read
Detailed Register Description
MFAE
address: 0D
address: 1A
MFRW
PEB 20550
PEF 20550
250 s, is
bit 0
H
H
MFFE
01.96