PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 268

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

W:MAAR
W:MACR
Upstream: CFI port 3, timeslot 7, bits 3 … 2 to PCM port 0, timeslot 4, bits 5 … 4
W:MADR
W:MAAR
W:MACR
The following sequence sets transmit timeslot 4 of PCM port 0 bits 5 … 4 and 1 … 0 to
low impedance and bits 7 … 6 and 3 … 2 to high impedance:
W:MADR
W:MAAR
W:MACR
Downstream: CFI port 2, timeslot 7, bits 3 … 0 from PCM port 1, timeslot 3, bits 7 … 4
W:MADR
W:MAAR
W:MACR
Examples
In PCM mode 0 and CFI mode 0 the following connections shall be programmed:
Upstream: CFI port 0, timeslot 3, bits 1 … 0 to PCM port 0, timeslot 4, bits 1 … 0
W:MADR
Semiconductor Group
= 1001 0000
= 1000 1001
= 0111 0100
= 1001 0000
= 1001 1111
= 0111 0110
= 0000 0101
= 1001 0000
= 0110 0000
= 0000 1011
= 0001 1101
= 0111 0011
B
B
B
B
B
B
B
B
B
B
B
B
PCM timeslot encoding, the subchannel position is
defined by MACR:CMC3 … 0 = 0100
CFI timeslot encoding, the subchannel position is
defined by CSCR:SC01 … 00 = 11
CM code for switching a 16 kBit/s/bits 1 … 0
channel (0100)
PCM timeslot encoding, the subchannel position is
defined by MACR:CMC3 … 0 = 0110
CFI timeslot encoding, the subchannel position is
defined by CSCR:SC31 … 30 = 10
CM code for switching a 16 kBit/s, bits 3 … 2
channel (0110)
bits 5, 4, 1, 0 to low Z and bits 7, 6, 3, 2 to high Z
PCM timeslot encoding
MOC code to access the tristate field
PCM timeslot encoding, the subchannel position is
defined by MACR:CMC3 … 0 = 0011
CFI timeslot encoding, the subchannel position is
defined by CSCR:SC21 … 20 = 01
CM code for switching a 32 kBit/s/bits 7 … 4
channel (0011)
268
Application Hints
PEB 20550
PEF 20550
01.96