PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 101

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

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Figure 50
Interrupt Driven Transmission Sequence Example
3.6.2
Prior to data transmission, the length of the frame to be transmitted must be
programmed via the Transmit Byte Count Registers (XBCH, XBCL). The resulting byte
count equals the programmed value plus one byte. Since 12 bits are provided via XBCH,
XBCL (XBC11
Having written the Transmit Byte Counter Registers, data transmission can be initiated
by command XTF/XPD or XDD. The SACCO will then autonomously request the correct
amount of write bus cycles by activating the DRQT-line. Depending on the programmed
frame length, block data transfers of n
the 32 byte transmit pool is accessible to the DMA-controller.
The following figure gives an example of a DMA driven transmission sequence with a
frame length of 70 bytes, i.e. programmed transmit byte count (XCNT) equal 69 bytes.
Figure 51
DMA Driven Transmission Example
Semiconductor Group
Serial
Interface
SACCO
CPU
Interface
Serial
Interface
SACCO
CPU
Interface
Data Transmission in DMA-Mode
XCNT = 69
32 Bytes
WR
WR;
XBC0) a frame length between 1 and 4096 bytes can be selected.
XTF
XTF
XPR
DRQT (32)
32 Bytes
WR
WR
32
Command
32-bytes + remainder are requested every time
XTF
Transmit Frame (70 Bytes)
101
DRQT (32)
WR
32
XPR
Transmit Frame (70 Bytes)
DRQT (6)
6 Bytes
WR
WR
32
Operational Description
32
XTF + XME
6
PEB 20550
6
PEF 20550
XPR
XPR
ITD05848
ITD08036
01.96