PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 324

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Figure 111
Access to PCM and CFI Data Using the Synchronous Transfer Utility
In upstream transmit direction (PCM interface output), it is necessary to assure that no
other data memory access writes to the same location in the upstream DM block. Hence
an upstream connection involving the same PCM port and timeslot as the synchronous
transfer may not be programmed.
An idle code previously written to the data or control memory for the upstream or
downstream directions is overwritten.
At the PCM interface it is possible to restrict the synchronous exchange with the data
registers STDA (STDB) to a 2 or 4 bit sub-timeslot position. The working principle is
similar to the subchannel switching described in chapter 5.4.2.
Semiconductor Group
Up-
stream
Down-
stream
2
1
SAXA/SAXB: 1
SARA/SARB:
CFI
Frame
0
127
0
127
Code Field
1
1 0
0
1
0
0
Control Memory
CFI Port + Time - Slot
CFI Port + Time - Slot
1
1
Data Field
STDA/STDB:
2
1
324
3
4
SAXA/SAXB:
SARA/SARB: 0
3
4
0
Data Memory
PCM Port + Time - Slot
PCM Port + Time - Slot
Data Field
Application Hints
PEB 20550
PEF 20550
PCM
Frame
0
127
0
127
Up-
stream
Down-
stream
ITD08091
01.96