PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 159

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Access in demultiplexed P-interface mode:
A logical 1 disables the corresponding interrupt as described in the ISTA-register.
A masked interrupt is stored internally and reported in ISTA immediately if the mask is
released. However, an SFI-interrupt is also reported in ISTA if masked. In this case no
interrupt is generated. When writing register MASK_E while ISTA_E indicates a non
masked interrupt INT is temporarily set into the inactive state.
SIN
SOV
4.6.31 Mask Register EPIC
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
TIN
Synchronous transfer Interrupt; The SIN-interrupt is enabled if at least one
synchronous transfer channel (A and/or B) is enabled via the STCR:TAE,
TBE-bits. The SIN-interrupt is generated when the access window for the P
opens. After the occurrence of the SIN-interrupt the P can read and/or write
the synchronous transfer data registers (STDA, STDB). The SIN-bit is reset
by reading ISTA.
Synchronous transfer Overflow; The SOV-interrupt is generated if the P
fails to access the data registers (STDA, STDB) within the access window.
The SOV-bit is reset by reading ISTA.
SFI
H
MFFI
®
-1 (MASK_E)
MAC
159
PFI
write
write
Detailed Register Description
PIM
address: 1C
address: 0E
SIN
PEB 20550
PEF 20550
bit 0
H
H
SOV
01.96