PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 219

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

CFI Framing Signal Output Control CMD2:FC2 … 0
This feature applies only if the configurable interface is clocked and synchronized via the
PCM interface clock and framing signals (PDC, PFS), i.e. if CMD1:CSS = 0.
In this case the ELIC delivers an output framing signal at pin FSC with a programmable
pulse width and position.
Note that the up- and downstream CFI frame position relative to the FSC output is not
affected by the setting of the CTAR and CBSR:CDS2 … 0 register bits.
Table 33 summarizes the 7 possible FSC Control (FC) modes:
Table 33
Applications of the Different Framing Control Modes
FC2
0
0
0
0
1
1
1
1
Semiconductor Group
FC1
0
0
1
1
0
0
1
1
FC0 FC
0
1
0
1
0
1
0
1
Mode
0
1
2
3
4
5
6
7
Main Applications
IOM-1 multiplexed (burst) mode
General purpose
General purpose
General purpose
Special SLD application
reserved
IOM-2, IOM-1 or SLD modes
Software timed multiplexed
IOM-2 applications
219
Notes
SBC, IBC, IEC-T
2 ISAC-S per SLD port
Standard IOM-2 setting;
no Superframes
generated
Standard IOM-2 setting;
Superframes generated
Application Hints
PEB 20550
PEF 20550
01.96