PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 154

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

The 9 byte deep CIFIFO stores the addresses of CFI time slots in which a C/I- and/or a
SIG-value change has taken place. This address information can then be used to read
the actual C/I- or SIG-value from the control memory.
SBV
SAD6..0
4.6.27 Timer Register (TIMR)
Access in demultiplexed P-interface mode:
The EPIC-1 timer can be used for 3 different purposes: timer interrupt generation
(ISTA:TIG), FSC multiframe generation (CMD2:FC2..0 = 111) and last look period
generation.
SSR
4.6.26 Signaling FIFO (CIFIFO)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 0xxxxxxx
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
bit 7
SSR
SBV
Signaling Byte Valid.
0… the SAD6..0 bits are invalid.
1… the SAD6..0 bits indicate a valid subscriber address. The polarity of SBV
Subscriber Address bits 6..0; The CM-address which corresponds to the CFI
time slot where a C/I- or SIG-value change has taken place is encoded in
these bits. For C/I-channels SAD6..0 point to an even CM-address (C/
I-value), for SIG-channels SAD6..0 point to an odd CM-address (stable SIG-
value).
Signaling Sampling Rate.
0… the last look period is defined by TVAL6..0.
1… the last look period is fixed to 125 s.
TVAL6
SAD6
is chosen such that the whole 8 bits of the CIFIFO can be copied to the
MAAR register in order to read the upstream C/I- or SIG-value from the
control memory.
H
B
TVAL5
SAD5
TVAL4
SAD4
154
TVAL3
SAD3
read
read
write
write
Detailed Register Description
TVAL2
SAD2
address: 18
address: 0C
address: 18
address: 0C
TVAL2
SAD1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
TVAL0
SAD0
01.96