PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 174

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

RC
RL6..0
4.7.10 Receive Length Check Register (RLCR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 0xxxxxxx
Semiconductor Group
bit 7
RC
Receive Check enable.
A ’1’ enables, a ’0’ disables the receive frame length feature.
Receive Length.
The maximum receive length after which data reception is suspended can be
programmed in RL6..0. The maximum allowed receive frame length is
(RL + 1)
aborted by the opposite station (RME-interrupt, RAB-bit set (VFR in clock
mode 3)).
In this case the receive byte count (RBCH, RBCL) is greater than the
programmed receive length.
RL6
32 bytes. A frame exceeding this length is treated as if it was
H
RL5
RL4
174
write
write
RL3
address: (Ch-A/Ch-B): 2E
address: (Ch-A/Ch-B): 5C
Detailed Register Description
RL2
RL1
PEB 20550
PEF 20550
bit 0
RL0
H
H
/6E
/DC
01.96
H
H