PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 258

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Reading the up- or
downstream DM data field
Summary of Memory Operations
Table 42
Summary of Control and Data Memory Commands
Application
Writing a PCM idle value to
the upstream DM data field
The MACR value specifies
the bandwidth and bit
position at the PCM
interface
Writing to a single tristate
field location
Writing to all tristate field
locations
Reading a single tristate
field location
Writing to the CM data field 8 bit value
Semiconductor Group
MADR
8 bit, 4 bit or 2 bit idle
value to be transmitted
at the PCM interface
8 bit value transmitted
at the upstream or 8 bit
value received at the
downstream PCM
interface
Tristate information
contained in the
4 LSBs:
0 = tristated,
1 = active
Tristate information
contained in the
4 LSBs:
0 = tristated,
1 = active
Tristate information
contained in the 4
LSBs
(C/I value, pointer to
PCM interface, etc.)
258
MAAR
Address of the
(upstream) PCM
port and timeslot
Address of the
PCM port and
timeslot
Address of the
(upstream) PCM
port and timeslot
Don’t care
Address of the
(upstream) PCM
port and timeslot
Address of the
CFI port and
timeslot
Application Hints
MACR (Hex)
08
18
10
38
30
28
20
88
60
68
E0
48
H
H
H
H
H
H
H
H
H
H
H
H
PEB 20550
PEF 20550
(bits 1 … 0)
(bits 7 … 0)
(bits 7 … 4)
(bits 3 … 0)
(bits 7 … 6)
(bits 5 … 4)
(bits 3 … 2)
01.96