PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 137

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

CMD1..0
CIS1..0
Semiconductor Group
CFI-Mode1,0.
Defines the actual number and configuration of the CFI-ports.
CMD1..0 CFI-
00
01
10
11
1)
where N = number of time slots in a PCM-frame
CFI Alternative Input Selection.
In CFI-mode 1 and 2 CIS1..0 controls the assignment between logical and
physical receive pins. In CFI-mode 0 and 3 CIS1,0 should be set to 0.
CFI-
Mode
0
1
2
3
In CFI-mode 0 data rate of 2.048 kBit/s can be used with a 2.048-kBit/s PDC-input clock, if
EMOD:ECMD2 = ’0’. Refer to chapter 4.5 ELIC-Mode Register (EMOD).
DU0
IN0
IN0
CIS0 = 0
IN
CIS0 = 0
I/O4
Mode
0
1
2
3
Port 0
Number
of
Logical
Ports
4 DU
(0..3)
2 DU
(0..1)
1 DU
8 bit (0..7) 128
DD0
OUT0
OUT0
OUT
I/O0
min.
128
128
128
CFI-Data Rate
DU1
IN1
IN1
CIS1 = 0
not active tristate
I/O5
[kBit/s]
max.
2048
4096
8192
1024
Port 1
137
DD1
OUT1
OUT1
I/O1
Min. Required
CFI-Data Rate
[kBit/s]
Relative to
PCM-Data Rate
32N/3
64N/3
64N/3
16N/3
DU2
IN2
IN0
CIS0 = 1
IN
CIS0 = 1
I/O6
Detailed Register Description
Port 2
Necessary
Reference
Clock (RCL)
2xDR
DR
0.5xDR
4xDR
DD2
OUT2
tristate
tristate
I/O2
DU3
IN3
IN1
CIS1 = 1
not active tristate
I/O7
DCL-Output
Frequencies
CMD1:CSS0 = 0
DR, 2xDR
DR
DR
DR, 2xDR
PEB 20550
PEF 20550
Port 3
DD3
OUT3
tristate
I/O3
1)
01.96