PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 289

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Table 46
Control Memory Codes for the Switching a 16 kBit/s CFI Channel to or from the
PCM Interface
Transferred Channel PCM
Bit Positions
Unassigned channel
16 kBit/s/ bits 7 … 6
16 kBit/s/ bits 5 … 4
16 kBit/s/ bits 3 … 2
16 kBit/s/ bits 1 … 0
logical 1; the MR and MX bit positions can then, if required, be accessed together with
the 4 bit C/I field via the even control memory address.
The D-Channel can be switched as a 16 kbps channel to and from the PCM interface in
order to be handled by a centralized D-Channel processing unit.
The 4 bit C/I channel can be accessed by the P for controlling layer-1 devices. In the
upstream direction each change in the C/I value is reported by interrupt to the P and
the CFI timeslot address is stored in the CIFIFO (refer to chapter 5.5.2). A C/I change
is detected if the value of the current CFI frame is different from the value of the previous
frame i.e. after at most 125 s.
To initialize two consecutive CFI timeslots for the decentral D-Channel handling scheme,
the CM codes as given in table 45 must be used.
Table 45
Control Memory Codes and Data for the Central D-Channel Handling Scheme
CM Address
Even timeslot downstream
Odd timeslot downstream
Even timeslot upstream
Odd timeslot upstream
The switching codes specify the PCM sub-timeslot positions of the 16 kBit/s transfer.
Note that the 2 D bits are always located on bits 7 … 6 of a CFI timeslot, the
CSCR:SC#1, SC#0 bits must therefore be set to 00 (see chapter 5.4.2).
1)
Semiconductor Group
This code sets the D bits to high impedance
CM Code
1010
Switch. code
1000
Switch. code
Downstream CM Codes
1011
0111
0110
0101
0100
1)
289
CM Data
11 C/I 11
Pointer to PCM TS
XX C/I XX
Pointer to PCM TS
Upstream CM Codes
0000
0111
0110
0101
0100
B
Application Hints
B
PEB 20550
PEF 20550
01.96