PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 307

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

MF Channel Subscriber Address Register
MFSAR: MFTC1 MFTC0
The exchange of monitor data normally takes place with only one subscriber circuit at a
time. This register serves to point the MF handler to that particular CFI timeslot.
MFTC1 … 0:
SAD5 … 0:
CFI timeslot encoding of MFSAR derived from MAAR:
MFSAR: MFTC1 MFTC0 SAD5
MAAR:MA7 selects between upstream and downstream CM blocks. This information is
not required since the transfer direction is defined by CMDR (transmit or receive).
MAAR:MA0 selects between even and odd timeslots. This information is also not
required since MF channels are always located on even timeslots.
Semiconductor Group
bit 7
MAAR:
MF Channel Transfer Control 1 … 0; these bits, in addition to
CMDR:MFT1,0 and OMDR:MFPS control the MF channel transfer as
indicated in table 49.
Subscriber address 5 … 0; these bits define the addressed
subscriber. The CFI timeslot encoding is similar to the one used for
Control Memory accesses using the MAAR register (see figure 84).
MA7
MA6
SAD5
SAD4
MA5
SAD4
307
SAD3
MA4
write reset value:
SAD3
SAD2
MA3
SAD2
SAD1
MA2
Application Hints
SAD1
SAD0
MA1
undefined
PEB 20550
PEF 20550
bit 0
SAD0
MA0
01.96