PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 260

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

PEB 20550
PEF 20550
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5.4
Switched Channels
This chapter treats the switching functions between the CFI and PCM interfaces which
are programmed exclusively in the control memory. The switching functions of channels
which involve the P interface or which are programmed in the synchronous transfer
registers are treated in chapter 5.6 and chapter 5.7.
The ELIC is a non-blocking space and time switch for 128 channels per direction.
Switching is performed between the configurable (CFI) and the PCM interfaces. Both
interfaces provide up to 128 timeslots which can be split up into either 4 ports with up to
32 timeslots, 2 ports with up to 64 timeslots or 1 port with up to 128 timeslots. In all of
these cases each port consists of a separate transmit and receive line (duplex ports). On
the CFI side a bidirectional mode is also provided (CFI mode 3) which offers 8 ports with
up to 16 timeslots per port. In this case each timeslot of each port can individually be
programmed to be either input or output.
The timeslot numbering always ranges from 0 to N – 1 (N = number of timeslots/frame),
and each timeslot always consists of 8 contiguous bits. The bandwidth of a timeslot is
therefore always 64 kBit/s.
The ELIC can switch single timeslots (64 kBit/s channels), double timeslots (128 kBit/s
channels) and also 2 bit and 4 bit wide sub-timeslots (16 and 32 kBit/s channels). The
bits in a timeslot are numbered 7 through 0. On the serial interfaces (PCM and CFI), bit 7
is the first bit to be transmitted or received, bit 0 the last. If the P has access to the serial
data, bit 7 represents the MSB (D7) and bit 0 the LSB (D0) on the P bus.
The switching of 128 kBit/s channels implies that two consecutive timeslots starting with
an even timeslot number are used, e.g. PCM timeslots 22 and 23 can be switched as a
single 16 bit wide timeslot to CFI timeslots 4 and 5. Under these conditions it is
guaranteed that the involved timeslots are submitted to the same frame delay (also refer
to chapter 5.4.4).
The switching of channels with a data rate of 16 and 32 kBit/s is possible for the following
sub-timeslot positions within an 8 bit timeslot:
Semiconductor Group
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