PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 375

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

6.3
When using the ELIC SACCO-A HDLC controller in conjunction with the D-channel
arbiter there might be a critical situation when a RFIFO overflow occurs.
The situation can be managed by software solution.
The following text describes this situation and advices how to manage it. Please refer
also to page 82f.
Precondition for the Critical Situation:
The ELIC D-channel arbiter is activated to serve all D-channels (register
AMO:CCHM = 1, refer to chapter 4.8.1), that have been enabled in the DCE3..0
registers (refer to page 188f).
The ELIC SACCO-A receives a frame of one of the enabled D-channels, although there
is not enough space for the whole frame in its RFIFO. A previously generated RME
interrupt has not yet been served.
Figure 130
Semiconductor Group
Behaviour of the SACCO-A when a RFIFO Overflow Occurs
Selection
Full
Selection
Limited
Receive message complete command (CMDR = 80)
SACCO_A : Frame
End Indication
pended
Expect
Frame
Sus-
375
ELIC Reset or
Clock Mode <>3
R
SACCO_A :
Frame Indication
Receive
Frame
Clock Mode <>3
Application Notes
ITD08456
PEB 20550
PEF 20550
01.96