PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 210

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

recommended to program the PCM loop in the control memory (refer to
chapter 5.4.3.1).
If OMDR:PTL is set to logical 1, the test loop is enabled i.e. the physical transmit pins
TxD# are internally connected to the corresponding physical receive pins RxD#, such
that data transmitted over TxD# are internally looped back to RxD# and data externally
received over RxD# are ignored. The TxD# pins still output the contents of the upstream
data memory according to the setting of the tristate field.
Note that this loop back function can only work if the upstream and downstream bit shifts
match and if the port assignment (PMOD:AIS1 … 0) is such that a logical transmitter is
looped back to a logical receiver (e.g. the PTL loop cannot work in PCM mode 2!).
For normal operation OMDR:PTL should be set to logical 0 (test loop disabled).
Figure 65 illustrates the effect of the PTL bit:
PCM Test Loop OMDR:PTL
The PCM test loop function can be used for diagnostic purposes if desired. If however a
‘simple’ CFI to CFI connection (CFI
Figure 65
Effect of the OMDR:PTL Bit
Semiconductor Group
From Upstream
Data Memory
To Downstream
Data Memory
ELIC
R
PCM
210
OMDR : PTL
CFI loop) shall be established, it is
1
ITS08044
0
PCM Interface
TxD#
RxD#
Application Hints
PEB 20550
PEF 20550
01.96