PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 72

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

contains the second and RHCR the third byte following the opening flag (currently
received frame only). When using LAPD the high byte address recognition feature can
be used to restrict the frame reception to the selected SAPI-type.
Transparent Mode 0 (MODE:MDS1, MDS0, ADM = 100)
Characteristics: HDLC formatted, no address recognition, any message length, any
window size.
No address recognition is performed and each frame is stored in the RFIFO. RAL1
contains the first and RHCR the second byte following the opening flag (currently
received frame only).
Non-Auto-Mode (MODE:MDS1, MDS0 = 01)
Characteristics: HDLC formatted, 1-byte/2-byte address field, address recognition, any
message length, any window size.
All frames with valid address fields are stored in the RFIFO and an interrupt (RPF, RME)
is issued.
The HDLC-control field, data in the I-field and an additional status byte are stored in
RFIFO. The HDLC-control field and the status byte can also be read from the registers
RHCR, RSTA (currently received frame only!).
According to the selected address mode, the SACCO can perform 2-byte or 1-byte
address recognition.
Transparent Mode 1 (MODE:MDS1, MDS0, ADM = 101)
Characteristics: HDLC formatted, high byte address recognition, any message length,
any window size.
Only the high byte address field is compared with RAH1, RAH2 and the group address
(FC
Note: In non-auto-mode and transparent mode I-frames with wrong CRC or aborted
Semiconductor Group
H
, FE
frames are stored in RFIFO. In the attached RSTA-byte the CRC and RAB-bits are
set accordingly to indicate this situation.
H
). The whole frame except the first address byte is stored in RFIFO. RAL1
72
Functional Description
PEB 20550
PEF 20550
01.96