PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 151

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

The STCR-register bits are used to enable or disable the synchronous transfer utility and
to determine the sub time slot bandwidth and position if a PCM-interface time slot is
involved.
TAE, TBE Transfer Channel A (B) Enable.
CTA2..0
4.6.21 Synchronous Transfer Transmit Address Register B (SAXB)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The SAXB-register specifies for synchronous transfer channel B to which output
interface, port and time slot the serial data contained in the STDB-register is sent.
ISXB
MTXB6..0
4.6.22 Synchronous Transfer Control Register (STCR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00xxxxxx
Semiconductor Group
bit 7
bit 7
ISXB
TBE
Channel Type A (B); these bits determine the bandwidth of the channel and
the position of the relevant bits in the time slot acoording to the table below.
MTXB6
Interface Select Transmit for channel B.
0… selects the PCM-interface as the output interface for synchronous
1… selects the CFI-interface as the output interface for synchronous
number at the interface selected by ISXB according to tables 16 and 17:
MTXB6..0 = MA6..0.
1… enables the P transfer of the corresponding channel.
0… disables the P transfer of the corresponding channel.
P-Transfer Transmit Address for channel B; selects the port and time slot
TAE
H
channel B.
channel B.
B
MTXB5
CTB2
MTXB4
CTB1
151
MTXB3
CTB0
read/write
read/write
read/write
read/write
Detailed Register Description
MTXB2
CTA2
address: 08
address: 09
address: 10
address: 12
MTXB1
CTA1
PEB 20550
PEF 20550
bit 0
bit 0
H
H
H
H
MTXB0
CTA0
01.96