FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 92
FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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Functional Description
5.3
5.3.1
92
Figure 5-6. LPC Interface Diagram
LPC Bridge (with System and Management
Functions) (D31:F0)
The LPC Bridge function of the ICH4 resides in PCI Device 31:Function 0. In addition to the LPC
bridge function, D31:F0 contains other functional units including DMA, Interrupt Controllers,
Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and
functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are
described in their respective sections.
LPC Interface
The ICH4 implements an LPC interface as described in the LPC 1.0 specification. The LPC
interface to the ICH4 is shown in
are shown as optional, but peripherals are not required to do so.
ICH4
SUS_STAT#
GPI
PCI Bus
LFRAME#
(optional)
(optional)
(optional)
LAD[3:0]
LPCPD#
LDRQ#
LSMI#
Figure
5-6. Note that the ICH4 implements all of the signals that
PCI
CLK
PCI
RST#
Intel
Super I/O
®
82801DBM ICH4-M Datasheet
PCI
SERIRQ
PCI
PME#
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