FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 369

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.8.3
Intel
®
Table 9-10. ACPI and Legacy I/O Register Map
82801DBM ICH4-M Datasheet
Note: All reserved bits and registers will always return 0 when read, and will have no effect when written.
Power Management I/O Registers
Table 9-10
These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be
moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the
ACPI 1.0 specification, and use the same bit names.
PMBASE
4Ch
10h
51h
60h
+ Offset
08
28
2C
3A
3C
00
02
04
17
30
34
38
0Ch
14h
15h
16h
20h
40h
42h
44h
48h
4Eh
50h
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0Bh
1Fh
2Bh
01h
03h
07h
2Fh
33h
37h
39h
3Bh
3Fh
13h
4Dh
5Fh
7Fh
shows the registers associated with ACPI and Legacy power management support.
Power Management 1 Status
Power Management 1 Enable
Power Management 1 Control
Power Management 1 Timer
Reserved
Processor Control
Level 2 Register
Level 3 Register
Level 4 Register
Reserved
PM2 Control
General Purpose Event 0 Status
General Purpose Event 0 Enables
SMI# Control and Enable
SMI Status Register
Alternate GPI SMI Enable
Alternate GPI SMI Status
Reserved
Monitor SMI Status
Reserved
Device Trap Status
Trap Enable register
Bus Address Tracker
Bus Cycle Tracker
Intel
Reserved
Reserved for TCO Registers
®
SpeedStep™ Control Register
Register Name
PM1a_EVT_BLK+2
LPC Interface Bridge Registers (D31:F0)
PM1a_CNT_BLK
PM2a_CNT_BLK
PM1a_EVT_BLK
GPE0_BLK+4
ACPI Pointer
PMTMR_BLK
GPE0_BLK
P_BLK+4
P_BLK+5
P_BLK+6
P_BLK
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Last Cycle
Last Cycle
Default
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00h
01h
0
0
R/W-Special
R/W-Special
R/W, R/WC
R/W, R/WC
Attributes
R/WC, RO
R/W, WO,
R/W, WO
R/W, RO
R/WC
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
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