FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 145

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.5
Intel
®
Table 5-37. Causes of SMI# and SCI (Sheet 2 of 2)
82801DBM ICH4-M Datasheet
NOTES:
Dynamic Processor Clock Control
The ICH4 has extensive control for dynamically starting and stopping system clocks. The clock
control is used for transitions among the various S0/Cx states, and processor throttling. Each
dynamic clock control method is described in this section. The various Sleep states may also
perform types of non-dynamic clock control.
The ICH4 supports the ACPI C0, C1, C3, and C4 states.
The Dynamic processor clock control is handled using the following signals:
The C1 state is entered based on the processor performing an auto halt instruction. The C2 state is
entered based on the processor reading the Level 2 register in the ICH4.
The C3 state is entered based on the processor reading the Level 3 register in the ICH4. Note that
an Intel SpeedStep technology transition may appear to temporarily pass through a C3 state,
however it is a separate transition and documented separately in
The C4 state is entered based on the processor reading the Level 4 register in the ICH4, or by
reading the Level 3 register when the C4onC3_EN bit is set.
1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3. GBL_SMI_EN must be 1 to enable SMI.
4. EOS must be written to 1 to re-enable SMI for the next one.
Device monitors match address in
its range
SMBus Host Controller
SMBus Slave SMI message
SMBus SMBALERT# signal active
SMBus Host Notify message
received
BATLOW# assertion
Access microcontroller 62h/66h
SLP_EN bit written to 1
•
•
•
•
•
•
STPCLK#: Used to halt processor instruction stream.
C3_STAT#: Used to signal an AGP device that the system is about to enter, or has just exited a
C3 state.
STP_CPU#: Used to stop processor’s clock
CPUSLP#: Must be asserted prior to STP_CPU# (in stop grant mode)
DPSLP#: Used to force Deeper Sleep for processor.
DPRSLPVR: Used to lower voltage of VRM during C4 state and optional for S1-M.
Cause
SCI
Yes
No
No
No
No
No
No
No
SMI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
HOST_NOTIFY_INTREN
Host Controller Enabled
DEV[n]_TRAP_EN=1
SMI_ON_SLP_EN=1
Additional Enables
BATLOW_EN=1.
SMB_SMI_EN
MCSMI_EN
none
none
Section 5.12.9
Functional Description
SMI_ON_SLP_EN_STS
SMBus host status reg.
HOST_NOTIFY_STS
DEV[n]_TRAP_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
Where Reported
DEVMON_STS,
BATLOW_STS
MCSMI_STS
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