FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 403

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

10.1.4
10.1.5
Intel
®
82801DBM ICH4-M Datasheet
STS — Device Status Register (IDE—D31:F1)
Address Offset:
Default Value:
REVID—Revision ID Register (IDE—D31:F1)
Offset Address:
Default Value:
7:0
10:9
Bit
4:0
Bit
15
14
13
12
11
Bit
8
7
6
5
0
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Cleared by writing a 1 to it.
1 = Bus Master IDE interface function, as a master, generated a master-abort.
Reserved as 0 — RO.
Signaled Target Abort (STA) — R/WC.
0 = Cleared by writing a 1 to it.
1 = ICH4 IDE interface function is targeted with a transaction that the ICH4 terminates with a target
DEVSEL# Timing Status (DEV_STS) — RO.
01 =Hardwired; however, the ICH4 does not have a real DEVSEL# signal associated with the IDE
Data Parity Error Detected (DPED)— RO. Reserved as 0.
Fast Back to Back Capable (FB2BC)— RO. Reserved as 1.
User Definable Features (UDF)— RO. Reserved as 0.
66 MHz Capable (66MHZ_CAP)— RO. Reserved as 0.
Reserved
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as
1 = Enable. Note that the Base Address register for the Bus Master registers should be
NOTES:
1. Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently
2. When this bit is 0 and the IDE controller is in Native Mode, the Interrupt Pin Register (see
disable the Primary or Secondary I/O spaces.
Section
the masking is in place and the interrupt is still active when the masking ends, the interrupt will
be allowed to be asserted.
abort.
unit, so these bits have no effect.
the Bus Master IO registers.
programmed before this bit is set.
06
0280h
08h
See Bit Description
10.1.19) will be masked (the interrupt will not be asserted). If an interrupt occurs while
–
07h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
IDE Controller Registers (D31:F1)
R/WC, RO
16 bits
RO
8 bits
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