FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 466

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
466
15:14
11:10
Bit
13
12
9
8
7
Reserved — RW. Should be written to =00b.
Port Owner — RW. Default = 1b. This bit unconditionally goes to a 0 when the Configured Flag bit in
the CONFIGFLAG register makes a 0-to-1 transition.
System software uses this field to release ownership of the port to a selected host controller (in the
event that the attached device is not a high-speed device). Software writes a 1 to this bit when the
attached device is not a high-speed device. A 1 in this bit means that a companion host controller
owns and controls the port. For operational details, see Chapter 4 of the Enhanced Host Controller
Interface (EHCI) Specification for Universal Serial Bus .
Port Power (PP)  RO. Hardwired to 1. This indicates that the port does have power.
Line Status — RO.These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal
lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable
sequence. This field is valid only when the port enable bit is 0 and the current connect status bit is
set to a 1.
00 = SE0
10 = J-state
01 = K-state
11 = Undefined
Reserved. This bit will return a 0 when read.
Port Reset — RW. When software writes a 1 to this bit (from a 0), the bus reset sequence as
defined in the Universal Serial Bus (USB) Specification, Revision 2.0 is started. Software writes a 0
to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long enough to
ensure the reset sequence completes, as specified in the Universal Serial Bus (USB) Specification ,
Revision 2.0 .
0 = Port is not in Reset. (Default)
1 = Port is in Reset.
NOTE: When software writes this bit to a 1, it must also write a 0 to the Port Enable bit. When
Warning: System software should not attempt to reset a port if the HCHalted bit in the EHCI_STS
Suspend — RW.
0 = Port not in suspend state. (Default).
1 = Port in suspend state.
Port Enabled Bit and Suspend bit of this register define the port states as follows:
Bits [Port Enabled, Suspend]Port State
• When in suspend state, downstream propagation of data is blocked on this port, except for port
• The host controller will unconditionally set this bit to a 0 when software sets the Force Port
• If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is a 0) the
0X Disable
10 Enable
11 Suspend
reset. Note that the bit status does not change until the port is suspended and that there may be
a delay in suspending a port depending on the activity on the port.
Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host controller.
results are undefined.
software writes a 0 to this bit, there may be a delay before the bit status changes to a 0. The
bit status will not read as a 0 until after the reset has completed. If the port is in high-speed
mode after reset is complete, the host controller will automatically enable this port (e.g., set
the Port Enable bit to a 1). A host controller must terminate the reset and stabilize the state
of the port within 2 milliseconds of software transitioning this bit from 1 to 0.
For example: if the port detects that the attached device is high-speed during reset, then the
host controller must have the port in the enabled state within 2 ms of software writing this bit
to a 0. The HCHalted bit in the EHCI_STS register should be a 0 before software attempts
to use this bit. The host controller may hold Port Reset asserted to a 1 when the HCHalted
bit is a 1. This field is 0 if Port Power is 0.
register is a 1. Doing so will result in undefined behavior.
Description
Intel
®
82801DBM ICH4-M Datasheet