FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 404

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

IDE Controller Registers (D31:F1)
10.1.6
10.1.7
10.1.8
404
PI — Programming Interface Register (IDE—D31:F1)
Address Offset:
Default Value:
SCC — Sub Class Code Register (IDE—D31:F1)
Address Offset:
Default Value:
BCC — Base Class Code Register (IDE—D31:F1)
Address Offset:
Default Value:
6:4
7:0
7:0
Bit
Bit
Bit
7
3
2
1
0
This read-only bit is a 1 to indicate that the ICH4 supports bus master operation
Reserved. Will always return 0.
SOP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the secondary controller supports
both legacy and native modes.
SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary IDE channel
is operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
POP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the primary controller supports
both legacy and native modes.
POP_MODE_SEL — R/W. This read/write bit determines the mode that the primary IDE channel is
operating in.
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
Sub Class Code — RO.
01h = IDE device, in the context of a mass storage device.
Base Class Code — RO.
01 = Mass storage device
09h
0Ah
0Bh
8Ah
01h
01h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
R/W
8 bits
RO
8 bits
RO
8 bits
®
82801DBM ICH4-M Datasheet