FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 286
FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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LAN Controller Registers (B1:D8:F0)
7.2.11
7.2.12
286
General Control Register
Offset Address:
Default Value:
General Status Register
Offset Address:
Default Value:
7:4
7:3
Bit
Bit
3
2
1
0
2
1
0
Reserved. These bits should be set to 0000b.
LAN Connect Software Reset
0 = Cleared by software to begin normal LAN Connect operating mode. Software must not attempt
1 = Software can set this bit to force a reset condition on the LAN Connect interface.
Reserved. This bit should be set to 0.
Deep Power-Down on Link Down Enable
0 = Disable
1 = The ICH4’s internal LAN Controller may enter a deep power-down state (sub-3 mA) in the D2
Reserved
Reserved
Duplex Mode — RO. This bit indicates the wire duplex mode.
0 = Half duplex
1 = Full duplex
Speed — RO. This bit indicates the wire speed.
0 = 10 Mbps
1 = 100 Mbps
Link Status Indication — RO. This bit indicates the status of the link.
0 = Invalid
1 = Valid
to access the LAN Connect interface for at least 1 ms after clearing this bit.
and D3 power states while the link is down. In this state, the LAN Controller does not keep link
integrity. This state is not supported for point-to-point connection of two end stations.
1Dh
1Ch
00h
h
—
R/W.
Description
Description
—
Attribute:
Size:
Attribute:
Size:
R/W.
Intel
®
82801DBM ICH4-M Datasheet
R/W
8 bits
RO
8 bits
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