FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 499
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FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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14.1.20
14.1.21
14.1.22
Intel
®
82801DBM ICH4-M Datasheet
CFG—Configuration Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This
register is not affected by the D3
PID—PCI Power Management Capability ID Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
PC—Power Management Capabilities Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register is not affected by the D3
15:11
15:8
10:9
7:1
7:0
Bit
Bit
Bit
8:6
2:0
0
5
4
3
Reserved — RO.
I/O Space Enable (IOSE) — R/W.
0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h become read
1 = Enable. BIOS must explicitly set this bit to allow a legacy driver to work.
Next Capability (NEXT) — RO. This field indicates that the next item in the list is at offset 00h.
Capability ID (CAP) — RO. This field indicates that this pointer is a message signaled interrupt
capability.
PME Support — RO. This field indicates PME# can be generated from all D states.
Reserved.
Auxiliary Current — RO. This field reports 375 mA maximum Suspend well current required when in
the D3cold state.
Device Specific Initialization (DSI) — RO. This bit indicates that no device-specific initialization is
required.
Reserved — RO.
PME Clock — RO. This bit indicates that PCI clock is not required to generate PME#.
Version — RO. Indicates support for Revision 1.1 of the PCI Power Management Specification.
only registers. (Default)
41h
00h
No
50h
0001h
No
52h
C9C2h
No
HOT
to D0 transition.
HOT
to D0 transition.
Description
Description
Description
AC ’97 Audio Controller Registers (D31:F5)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
8 bits
Core
RO
16 bits
Core
RO
16 bits
Core
499
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