FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 248

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.19.2.3
5.19.2.4
5.19.2.5
5.19.2.6
5.19.2.7
5.19.2.8
248
Output Slot 1: Command Address Port
The command port is used to control features and monitor status of AC ‘97 functions including, but
not limited to, mixer settings and power management.
The control interface architecture supports up to 64, 16-bit read/write registers, addressable on
even byte boundaries. Only the even registers (00h, 02h, etc.) are valid.
Output frame slot 1 communicates control register address, and write/read command information.
In the case of the multiple codec implementation, accesses to the codecs are differentiated by the
driver using address offsets 00h
secondary codec, and address offsets 100h
link, however, is done via the codec ID bits. See
Output Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle as indicated in slot 1, bit 19. If the current
command port operation is a read then the entire slot time stuffed with 0s by the ICH4. Bits [19:4]
contain the write data. Bits [3:0] are reserved and are stuffed with 0s.
Output Slot 3: PCM Playback Left Channel
Output frame slot 3 is the composite digital audio left playback stream. Typically, this slot is
composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH4
transmits sample streams of 16 bits or 20 bits and stuffs remaining bits with zeros.
Data in output slots 3 and 4 from the ICH4 should be duplicated by software if there is only a single
channel out.
Output Slot 4: PCM Playback Right Channel
Output frame slot 4 is the composite digital audio right playback stream. Typically, this slot is
composed of standard PCM (.wav) output samples digitally mixed by the host processor. The ICH4
transmits sample streams of 16 or 20 bits and stuffs remaining bits with 0s.
Data in output slots 3 and 4 from the ICH4 should be duplicated by software if there is only a single
channel out.
Output Slot 5: Modem Codec
Output frame slot 5 contains modem DAC data. The modem DAC output supports 16-bit
resolution. At boot time, if the modem codec is supported, the AC ’97 controller driver determines
the DAC resolution. During normal runtime operation the ICH4 stuffs trailing bit positions within
this time slot with zeros.
Output Slot 6: PCM Playback Center Front Channel
When set up for 6-channel mode, this slot is used for the front center channel. The format is the
same as Slots 3 and 4. If not set up for 6-channel mode, this channel will always be stuffed with 0s
by ICH4.
–
7Fh for the primary codec, address offsets 80h
–
17Fh for the tertiary codec. The differentiation on the
Section 5.19.2.23
Intel
®
for further details.
82801DBM ICH4-M Datasheet
–
FEh for the