FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 449

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.1.28
Intel
®
82801DBM ICH4-M Datasheet
LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
Power Well:
28:22
12:6
Bit
31
30
29
21
20
19
18
17
16
15
14
13
SMI on BAR —R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = This bit is set to 1 whenever the Base Address Register (BAR) is written.
SMI on PCI Command — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = This bit is set to 1 whenever the PCI Command Register is written.
SMI on OS Ownership Change — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = HC OS Owned Semaphore bit in the USB EHCI Legacy Support Extended Capability register
Reserved — RO. Hardwired to 00h
SMI on Async Advance — RO. Shadow bit of the Interrupt on Async Advance bit in the EHCI_STS
register.
NOTE: To clear this bit system software must write a 1 to the Interrupt on Async Advance bit in the
SMI on Host System Error — RO. Shadow bit of Host System Error bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the Host System Error bit in the
SMI on Frame List Rollover — RO. Shadow bit of Frame List Rollover bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in the
SMI on Port Change Detect — RO. Shadow bit of Port Change Detect bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in the
SMI on USB Error — RO. Shadow bit of USB Error Interrupt (USBERRINT) bit in the EHCI_STS
register.
NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in the
SMI on USB Complete — RO. Shadow bit of USB Interrupt (USBINT) bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the EHCI_STS
SMI on BAR Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on BAR is 1, then the host controller will issue an SMI.
SMI on PCI Command Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PCI Command is 1, then the host controller will issue an
SMI on OS Ownership Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit is 1, the host controller will
Reserved — RO. Hardwired to 00h
transitioned from 1-to-0 or 0-to-1.
SMI.
issue an SMI.
EHCI_STS register.
EHCI_STS register.
EHCI_STS register.
EHCI_STS register.
EHCI_STS register.
register.
Suspend
6C
00000000h
–
6Fh
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W, R/WC, RO
32 bits
449