FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 343

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.4.7
Intel
®
82801DBM ICH4-M Datasheet
OCW2—Operational Control Word 2 Register
Offset Address:
Default Value:
Following a part reset or ICW initialization, the controller enters the fully nested mode of
operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI
mode are disabled following initialization.
7:5
4:3
2:0
Bit
Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and End of Interrupt
modes and combinations of the two.
000 = Rotate in Auto EOI Mode (Clear)
001 = Non-specific EOI command
010 = No Operation
011 = Specific EOI Command
100 = Rotate in Auto EOI Mode (Set)
101 = Rotate on Non-Specific EOI Command
110 = *Set Priority Command
111 = *Rotate on Specific EOI Command
*L0–L2 Are Used
OCW2 Select — WO. When selecting OCW2, bits 4:3 = 00
Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt level acted upon
when the SL bit is active. A simple binary code, outlined below, selects the channel for the command
to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2,
L1 and L0 to 0 is sufficient in this case.
BitsInterrupt LevelBitsInterrupt Level
000IRQ0/8100IRQ4/12
001IRQ1/9101IRQ5/13
010IRQ2/10110IRQ6/14
011IRQ3/11111IRQ7/15
Master Controller
Slave Controller
Bit[4:0]=undefined, Bit[7:5]=001
–
0A0h
–
020h
Description
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
WO
8 bits
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