FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 60

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.20
2.20.1
60
Table 2-20. Functional Strap Definitions
Pin Straps
Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of
PWROK to select configurations, and then revert later to their normal usage. To invoke the
associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled.
AC_SDOUT
EE_DOUT
GNT[A]#
DPRSLPVR
HICOMP
SPKR
Signal
Safe Mode
Reserved
Top-Block Swap
Override
No Reboot
SCHEME (HI 1.0
Hub Interface
Hub Interface
(correlated to
Termination
vs. HI 1.5)
HICOMP)
Scheme
Usage
Rising Edge of
PWROK
Rising Edge of
PWROK
Rising Edge of
PWROK
Rising Edge of
PWROK
Rising Edge of
PWROK
When Sampled
The signal has a weak internal pull-down. If the
signal is sampled high, the ICH4 will set the
processor speed strap pins for safe mode. Refer to
processor specification for speed strapping
definition. The status of this strap is readable via the
SAFE_MODE bit (bit 2, D31: F0, Offset D4h).
System designers should include a placeholder for a
pull-down resistor on EE_DOUT but do not
populate the resistor.
The signal has a weak internal pull-up. If the signal
is sampled low, this indicates that the system is
strapped to the “top-block swap” mode (Intel
will invert A16 for all cycles targeting FWH BIOS
space). The status of this strap is readable via the
Top_Swap bit (bit 13, D31: F0, Offset D4h). Note
that software will not be able to clear the Top-Swap
bit until the system is rebooted without GNT[A]#
being pulled down.
Low (default): Hub Interface 1.0 series or Hub
Interface 1.5 parallel termination.
High (external pull-up to VccHI): Not supported by
ICH4.
See the specific platform design guide for resistor
values and routing guidelines for each hub interface
mode.
Low (default due to weak internal pull-down): Hub
Interface 1.0 buffer mode (series termination) will be
selected.
High (external pullup to VccHI): Hub Interface 1.5
buffer mode (parallel termination) will be selected.
See the specific platform design guide for resistor
values and routing guidelines for each hub interface
mode.
The signal has a weak internal pull-down. If the
signal is sampled high, this indicates that the system
is strapped to the “No Reboot” mode (ICH4 will
disable the TCO Timer system reboot feature). The
status of this strap is readable via the NO_REBOOT
bit (bit 1, D31: F0, Offset D4h).
Intel
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82801DBM ICH4-M Datasheet
Comment
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ICH4