FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 388
FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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LPC Interface Bridge Registers (D31:F0)
9.8.3.21
388
Note: Writes to this register will initiate an Intel SpeedStep technology transition, which involves a
SS_CNT— Intel
Default Value
Lockable:
Power Well:
temporary transition to a C3-like state in which the STPCLK# signal will go active. An Intel
SpeedStep technology transition always occur on writes to the SS_CNT register, even if the value
written to SS_STATE is the same as the previous value (after this “transition” the system would
still be in the same Intel SpeedStep technology state). If the SS_EN bit is 0, then writes to this
register will have no effect and reads will return 0.
I/O Address:
7:1
Bit
0
Reserved
Intel SpeedStep technology State (SS_STATE) — R/W (Special). When this bit is read, it will
return the current Intel SpeedStep technology state. Writes to this register will cause a change to the
Intel SpeedStep technology state indicated by the value written to this bit.
0 = High power state.
1 = Low power state.(default)
PMBASE +50h
No
Core
01h
®
SpeedStep
®
Control Register
Description
Attribute:
Size:
Usage:
Intel
®
82801DBM ICH4-M Datasheet
R/W (special)
8 bit
ACPI/Legacy
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