FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 194
FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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Functional Description
5.16.2.3
194
Table 5-64. Command Register, Status Register, and TD Status Bit Interaction
Command Register, Status Register, and TD Status Bit Interaction
NOTES:
Note that if a NAK or STALL response is received from a SETUP transaction, a Time Out Error
will be reported. This causes the Error counter to decrement and the CRC/Time-out Error status bit
to be set within the TD Control and Status DWord during write back. If the Error counter changes
from 1 to 0, the Active bit is reset to 0 and Stalled bit to 1 as normal.
1. Only If error counter counted down from 1 to 0
2. Suspend mode can be entered only when Run/Stop bit is 0
CRC/Time Out Error
Illegal PID, PID Error,
Max Length (illegal)
PCI Master/Target Abort
Suspend Mode
Resume Received and
Suspend Mode = 1
Run/Stop = 0
Configuration Flag Set
HC Reset/Global Reset
IOC = 1 in TD Status
Stall
Bit Stuff/Data Buffer Error
Short Packet Detect
Condition
Intel
Set USB Error Int bit
Clear Run/Stop bit in Command register
Set HC Process Error and HC Halted bits
Clear Run/Stop bit in Command register
Set Host System Error and HC Halted bits
Clear Run/Stop bit in Command register
Set HC Halted bit
Set Resume received bit
Clear Run/Stop bit in command register
Set HC Halted bit
Set Configuration Flag in Command
register
Clear Run/Stop and Configuration Flag in
Command register
Clear USB Int, USB Error Int, Resume
received, Host System Error, HC Process
Error, and HC Halted bits
Set USB Int bit
Set USB Error Int bit
Set USB Error Int bit
Set USB Int bit
®
ICH4 USB Status Register Actions
1
1
, Clear HC Halted bit
2
Intel
Clear Active bit
Clear Active bit
Clear Active bit
Clear Active bit
®
82801DBM ICH4-M Datasheet
TD Status Register Actions
1
1
1
and set Stall bit
and set Stall bit
and set Stall bit
1
1
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