FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 340

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.4.1
340
ICW1—Initialization Command Word 1 Register
Offset Address:
Default Value:
A write to Initialization Command Word 1 starts the interrupt controller initialization sequence,
during which the following occurs:
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the
initialization sequence.
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special mask mode is cleared and Status Read is set to IRR.
Bit
7:5
4
3
2
1
0
ICW/OCW Select — WO. These bits are MCS-85 specific, and not needed.
000 = Should be programmed to 000
ICW/OCW Select — WO.
1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence.
Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level triggered control
registers (ELCR).
ADI — WO.
0 = Ignored for the ICH4. Should be programmed to 0.
Single or Cascade (SNGL) — WO.
0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.
ICW4 Write Required (IC4) — WO.
1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.
Master Controller
All bits undefined
Slave Controller
–
0A0h
–
020h
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
WO
8 bit /controller