FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 474
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FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
Lead Free Status / RoHS Status
Not Compliant
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SMBus Controller Registers (D31:F3)
13.1.2
13.1.3
474
DID—Device Identification Register (SMBUS—D31:F3)
Address:
Default Value:
CMD—Command Register (SMBUS—D31:F3)
Address:
Default Value:
15:10
15:0
Bit
Bit
9
8
7
6
5
4
3
2
1
0
Device Identification Value — RO.
Reserved
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — RO. Reserved as 0.
Memory Space Enable (MSE) — RO. Reserved as 0.
I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.
02–03h
24C3h
04–05h
0000h
Description
Description
Attribute:
Size:
Attributes:
Size:
Intel
®
82801DBM ICH4-M Datasheet
RO
16 bits
RO R/W
16 bits
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