FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 9

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
5.13
5.14
5.15
5.12.9 Intel
5.12.10 Event Input Signals and Their Usage .............................................157
5.12.11 ALT Access Mode...........................................................................159
5.12.12 System Power Supplies, Planes, and Signals ................................163
5.12.13 Clock Generators ............................................................................165
5.12.14 Legacy Power Management Theory of Operation ..........................166
System Management (D31:F0)....................................................................167
5.13.1 Theory of Operation ........................................................................167
5.13.2 Alert on LAN* ..................................................................................168
General Purpose I/O ....................................................................................173
5.14.1 GPIO Mapping ................................................................................173
5.14.2 Power Wells ....................................................................................174
5.14.3 SMI# and SCI Routing ....................................................................174
IDE Controller (D31:F1) ...............................................................................175
5.15.1 PIO Transfers..................................................................................175
5.12.8.2 THRM# Initiated Passive Cooling....................................154
5.12.8.3 THRM# Override Software Bit .........................................154
5.12.8.4 Processor-Initiated Passive Cooling (Via Programmed
5.12.8.5 Active Cooling..................................................................155
5.12.9.1 Intel SpeedStep Technology Processor Requirements...156
5.12.9.2 Intel SpeedStep Technology States ................................156
5.12.9.3 Voltage Regulator Interface.............................................156
5.12.10.1 PWRBTN# - Power Button ..............................................157
5.12.10.2 Ring Indicate (RI#)...........................................................158
5.12.10.3 PCI Power Management Event (PME#) ..........................158
5.12.10.4 SYS_RESET# Signal ......................................................158
5.12.10.5 THRMTRIP# Signal .........................................................159
5.12.10.6 AGPBUSY# .....................................................................159
5.12.11.1 Write Only Registers with Read Paths in ALT Access
5.12.11.2 PIC Reserved Bits ...........................................................162
5.12.11.3 Read Only Registers with Write Paths in ALT Access
5.12.12.1 Power Plane Control with SLP_S3#, SLP_S4# and
5.12.12.2 SLP_S1# Signal ..............................................................163
5.12.12.3 PWROK Signal ................................................................163
5.12.12.4 VRMPWRGD Signal........................................................164
5.12.12.5 VGATE Signal .................................................................164
5.12.12.6 BATLOW# - Battery Low .................................................164
5.12.12.7 Controlling Leakage and Power Consumption during
5.12.13.1 Clock Control Signals from ICH4 to Clock Synthesizer ...165
5.12.14.1 APM Power Management................................................166
5.13.1.1 Detecting a System Lockup.............................................167
5.13.1.2 Handling an Intruder ........................................................167
5.13.1.3 Detecting Improper FWH Programming ..........................168
5.13.1.4 Handling an ECC Error or Other Memory Error...............168
5.15.1.1 IDE Port Decode..............................................................175
5.15.1.2 IDE Legacy Mode and Native Mode................................175
5.15.1.3 PIO IDE Timing Modes....................................................177
5.15.1.4 IORDY Masking...............................................................177
5.15.1.5 PIO 32-Bit IDE Data Port Accesses ................................177
®
SpeedStep
Duty Cycle on STPCLK#) ................................................155
Mode................................................................................160
Mode................................................................................163
SLP_S5# .........................................................................163
Low-Power States ...........................................................164
®
Technology Protocol ........................................155
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