FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 7

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
5.6
5.7
5.8
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
5.5.9
5.5.10 General Flow of DMA Transfers .....................................................106
5.5.11 Terminal Count ...............................................................................107
5.5.12 Verify Mode.....................................................................................107
5.5.13 DMA Request Deassertion .............................................................107
5.5.14 SYNC Field / LDRQ# Rules ............................................................108
8254 Timers (D31:F0)..................................................................................109
5.6.1
5.6.2
8259 Interrupt Controllers (PIC) (D31:F0)....................................................112
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
Advanced Interrupt Controller (APIC) (D31:F0) ...........................................119
5.8.1
5.8.2
5.8.3
5.8.4
PCI DMA Expansion Cycles ...........................................................103
DMA Addresses ..............................................................................104
DMA Data Generation.....................................................................104
DMA Byte Enable Generation.........................................................104
DMA Cycle Termination ..................................................................105
LPC DMA ........................................................................................105
Asserting DMA Requests................................................................105
Abandoning DMA Requests............................................................106
Timer Programming ........................................................................109
Reading from the Interval Timer .....................................................110
5.6.2.1
5.6.2.2
5.6.2.3
Interrupt Handling ...........................................................................113
5.7.1.1
5.7.1.2
5.7.1.3
Initialization Command Words (ICWx) ............................................114
5.7.2.1
5.7.2.2
5.7.2.3
5.7.2.4
Operation Command Words (OCW) ...............................................115
Modes of Operation ........................................................................115
5.7.4.1
5.7.4.2
5.7.4.3
5.7.4.4
5.7.4.5
5.7.4.6
5.7.4.7
5.7.4.8
5.7.4.9
5.7.4.10 Automatic End of Interrupt Mode.....................................117
Masking Interrupts ..........................................................................118
5.7.5.1
5.7.5.2
Steering PCI Interrupts ...................................................................118
Interrupt Handling ...........................................................................119
Interrupt Mapping............................................................................119
APIC Bus Functional Description....................................................120
5.8.3.1
5.8.3.2
5.8.3.3
PCI Message-Based Interrupts.......................................................127
Simple Read ....................................................................110
Counter Latch Command ................................................111
Read Back Command .....................................................111
Generating Interrupts.......................................................113
Acknowledging Interrupts ................................................113
Hardware/Software Interrupt Sequence ..........................114
ICW1................................................................................114
ICW2................................................................................115
ICW3................................................................................115
ICW4................................................................................115
Fully Nested Mode...........................................................115
Special Fully-Nested Mode..............................................116
Automatic Rotation Mode (Equal Priority Devices)..........116
Specific Rotation Mode (Specific Priority) .......................116
Poll Mode.........................................................................116
Cascade Mode ................................................................117
Edge and Level Triggered Mode .....................................117
End of Interrupt Operations .............................................117
Normal End of Interrupt ...................................................117
Masking on an Individual Interrupt Request ....................118
Special Mask Mode .........................................................118
Physical Characteristics of APIC .....................................120
APIC Bus Arbitration........................................................120
Bus Message Formats.....................................................121
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