FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 135
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FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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Intel
®
Table 5-29. Configuration Bits Reset By RTCRST# Assertion
82801DBM ICH4-M Datasheet
Note: Both the GPI and SAFEMODE strap techniques to clear CMOS require multiple steps to
Note: Clearing CMOS, using a jumper on VCCRTC, must not be implemented.
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this
GPI on system boot-up, and manually clear the CMOS array.
Using the SAFEMODE Strap to Clear CMOS
A jumper on AC_SDOUT (SAFEMODE strap) can also be used to clear CMOS values. BIOS
would detect the setting of the SAFE_MODE status bit (D31:F0: Offset D4h bit 2) on system boot-
up, and manually clear the CMOS array.
implement. The system is booted with the jumper in new position, then powered back down. The
jumper is replaced back to the normal position, then the system is rebooted again. The RTCRST#
jumper technique allows the jumper to be moved and then replaced, all while the system is
powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state.
FREQ_STRAP[3:0]
AIE
AF
PWR_FLR
AFTERG3_EN
RTC_PWR_STS
PRBTNOR_STS
PME_EN
RI_EN
NEW_CENTURY_STS
INTRD_DET
TOP_SWAP
RTC_EN
BATLOW_EN
Bit Name
GEN_STS
RTC Reg B
RTC Reg C
GEN_PMCON_3
GEN_PMCON_3
GEN_PMCON_3
PM1_STS
GPE0_EN
GPE0_EN
TCO2_STS
GEN_STS
PM1_EN
GPE0_EN
TCO1_STS
Default State
D31:F0:D4h
I/O space
I/O space
D31:F0:A4h
D31:F0:A4h
D31:F0:A4h
PMBase + 00h
PMBase + 2Ah
PMBase + 2Ah
TCOBase + 04h
TCOBase + 06h
D31:F0:D4h
PMBase + 02h
PMBase + 2Ah
Register
Location
Functional Description
11:8
11
11
13
10
10
5
1
0
8
5
2
7
0
Bit(s)
1111b
0
0
0
0
1
0
0
0
0
0
0
0
0
135
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