FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 412

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

IDE Controller Registers (D31:F1)
10.1.23
412
Note: For FAST_SCB1=1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to
SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)
Address Offset:
Default Value:
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Bit
Reserved
Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)SCB1 = 1 (66 MHz clk)FAST_SCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks00 = Reserved00 = Reserved
01 = CT 3 clocks, RP 5 clocks01 = CT 3 clocks, RP 8 clocks01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks10 = CT 2 clocks, RP 8 clocks10 = Reserved
11 = Reserved11 = Reserved11 = Reserved
Reserved
Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)SCB1 = 1 (66 MHz clk)FAST_SCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks00 = Reserved00 = Reserved
01 = CT 3 clocks, RP 5 clocks01 = CT 3 clocks, RP 8 clocks01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks10 = CT 2 clocks, RP 8 clocks10 = Reserved
11 = Reserved11 = Reserved11 = Reserved
Reserved
Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)PCB1 = 1 (66 MHz clk)FAST_PCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks00 = Reserved00 = Reserved
01 = CT 3 clocks, RP 5 clocks01 = CT 3 clocks, RP 8 clocks01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks10 = CT 2 clocks, RP 8 clocks10 = Reserved
11 = Reserved11 = Reserved11 = Reserved
Reserved
Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)PCB1 = 1 (66 MHz clk)FAST_PCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks00 = Reserved00 = Reserved
01 = CT 3 clocks, RP 5 clocks01 = CT 3 clocks, RP 8 clocks01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks10 = CT 2 clocks, RP 8 clocks10 = Reserved
11 = Reserved11 = Reserved11 = Reserved
4A
0000h
–
4Bh
Description
Attribute:
Size:
Intel
R/W
16 bits
®
82801DBM ICH4-M Datasheet
Section 5.15.6
for details.