FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 520
FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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AC ’97 Modem Controller Registers (D31:F6)
15.1.12
15.1.13
15.1.14
520
SVID—Subsystem Vendor ID (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
The SVID register, in combination with the Subsystem ID register, enable the operating
environment to distinguish one audio subsystem from the other(s). This register is implemented as
a write-once register. Once a value is written to it, the value can be read back. Any subsequent
writes will have no effect. This register is not affected by the D3
SID—Subsystem ID (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
The SID register, in combination with the Subsystem Vendor ID register make it possible for the
operating environment to distinguish one audio subsystem from another. This register is
implemented as write-once register. Once a value is written to it, the value can be read back. Any
subsequent writes will have no effect.
This register is not affected by the D3
CAP_PTR—Capabilities Pointer (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
This register indicates the offset for the capability pointer.
7:0
Bit
15:0
15:0
Bit
Bit
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer offset is
offset 50h.
Subsystem Vendor ID — R/Write-Once.
Subsystem ID — R/Write-Once.
0000h
0000h
34h
2C
No
2E
No
50h
No
–
–
2Fh
2Dh
HOT
to D0 transition.
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
HOT
®
82801DBM ICH4-M Datasheet
to D0 transition.
R/WO
16 bits
Core
R/WO
16 bits
Core
RO
8 bits
Core
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