FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 590

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Table A-1. Intel
590
Capability ID Register
Next Item Pointer
Power Management Capabilities
Power Management Control/Status
Register
Data Register
Vendor ID
Device ID
PCI Device Command Register
PCI Device Status Register
Revision ID
Sub Class Code
Base Class Code
Primary Master Latency Timer
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Master Latency Timer
IO Base Register
IO Limit Register
Secondary Status Register
Memory Base
Memory Limit
Register Name
®
ICH4 PCI Configuration Registers (Sheet 2 of 10)
DE–DFh
E0–E1h
1E–1Fh
00–01h
02–03h
04–05h
06–07h
20–21h
22–23h
Offset
DCh
DDh
E2h
0Ah
0Bh
0Dh
0Eh
1Ah
1Bh
1Ch
1Dh
08h
18h
19h
Hub Interface to PCI Bridge D30:F0
Section 7.1.20, “CAP_ID — Capability ID Register (LAN Controller—
B1:D8:F0)” on page 7-273
Section 7.1.21, “NXT_PTR — Next Item Pointer (LAN Controller—
B1:D8:F0)” on page 7-273
Section 7.1.22, “PM_CAP — Power Management Capabilities (LAN
Controller—B1:D8:F0)” on page 7-274
Section 7.1.23, “PMCSR — Power Management Control/Status Register
(LAN Controller—B1:D8:F0)” on page 7-274
Section 7.1.24, “PCIDATA — PCI Power Management Data Register (LAN
Controller—B1:D8:F0)” on page 7-275
Section 8.1.1, “VID—Vendor ID Register (HUB-PCI—D30:F0)” on
page 8-290
Section 8.1.2, “DID—Device ID Register (HUB-PCI—D30:F0)” on
page 8-290
Section 8.1.3, “CMD—Command Register (HUB-PCI—D30:F0)” on
page 8-291
Section 8.1.4, “PD_STS—Primary Device Status Register (HUB-PCI—
D30:F0)” on page 8-292
Section 8.1.5, “RID—Revision Identification Register (HUB-PCI—D30:F0)”
on page 8-293
Section 8.1.6, “SCC—Sub-Class Code Register (HUB-PCI—D30:F0)” on
page 8-293
Section 8.1.7, “BCC—Base-Class Code Register (HUB-PCI—D30:F0)” on
page 8-293
Section 8.1.8, “PMLT—Primary Master Latency Timer Register (HUB-
PCI—D30:F0)” on page 8-293
Section 8.1.9, “HEADTYP—Header Type Register (HUB-PCI—D30:F0)”
on page 8-294
Section 8.1.10, “PBUS_NUM—Primary Bus Number Register (HUB-PCI—
D30:F0)” on page 8-294
Section 8.1.11, “SBUS_NUM—Secondary Bus Number Register (HUB-
PCI—D30:F0)” on page 8-294
Section 8.1.12, “SUB_BUS_NUM—Subordinate Bus Number Register
(HUB-PCI—D30:F0)” on page 8-294
Section 8.1.13, “SMLT—Secondary Master Latency Timer Register (HUB-
PCI—D30:F0)” on page 8-295
Section 8.1.14, “IOBASE—I/O Base Register (HUB-PCI—D30:F0)” on
page 8-295
Section 8.1.15, “IOLIM—I/O Limit Register (HUB-PCI—D30:F0)” on
page 8-295
Section 8.1.16, “SECSTS—Secondary Status Register (HUB-PCI—
D30:F0)” on page 8-296
Section 8.1.17, “MEMBASE—Memory Base Register (HUB-PCI—
D30:F0)” on page 8-297
Section 8.1.18, “MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)”
on page 8-297
Datasheet Location
Intel
®
82801DBM ICH4-M Datasheet
Register Index