EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 85
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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DS785UM1
[31:28]
Cond
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
Table 3-5
The remaining bits in the instruction formats are interpreted as follows:
Mnemonic
Extension
• opcode1: MaverickCrunch co-processor-defined opcode
• opcode2: MaverickCrunch co-processor defined opcode
• CRn: MaverickCrunch co-processor-defined register
• CRd: MaverickCrunch co-processor-defined register
• CRm: MaverickCrunch co-processor-defined register
• Rn: Specifies an ARM base address register. These bits are ignored by the
• Rd: Specifies a source or destination ARM register
• cp_num: Co-processor number
• P: Pre-indexing (P=1) or post-indexing (P=0) addressing. This bit is ignored by the
• U: Specifies whether the supplied 8-bit offset is added to a base register (U=1) or
• N: Specifies the width of a data type involved in a move operation. The MaverickCrunch
CS/HS
CC/LO
EQ
NE
VC
GE
NV
PL
VS
LS
GT
LE
AL
MI
LT
HI
MaverickCrunch co-processor.
MaverickCrunch co-processor.
subtracted from a base register (U=0). This bit is ignored by the MaverickCrunch co-
processor.
shows the condition codes, which are bits [31:28] for each instruction format.
Carry Set/Unsigned Higher or Same
Signed Greater Than or Equal
Carry Clear/Unsigned Lower
Signed Less Than or Equal
Unsigned Lower or Same
Always (unconditional)
Plus/Positive or Zero
Signed Greater Than
Signed Less Than
Unsigned Higher
Minus/Negative
No Overflow
Meaning
Not Equal
Overflow
Never
Equal
Table 3-5. Condition Code Definitions
Copyright 2007 Cirrus Logic
Z clear, and either N set and V set, or N clear and V clear (Z = 0, N = V)
Z set, or N set and V clear, or N clear and V set (Z = 1, N ! = V)
N set and V clear, or N clear and V set (N ! = V)
N set and V set, or N clear and V clear (N = V)
Status Flag State
C set and Z clear
C clear or Z set
Z clear
C clear
N clear
V clear
C set
N set
V set
Z set
MaverickCrunch Co-Processor
-
-
EP93xx User’s Guide
3-15
3
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