EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 652
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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20
20.1 Registers
Register Descriptions
RTCData
20-4
Real Time Clock With Software Trim
EP93xx User’s Guide
20.1.2 Reset Control
31
15
Address:
Default:
Definition:
Bit Descriptions:
The RTC block level reset operation is a bit complicated. The reset strategy is for the time-
keeping part of the RTC to survive a system reset, and only be initialized by a power-on reset.
The RTC interrupt enable is cleared by a user reset, so that a time count match (alarm
interrupt) would disable with system reset.
The following register is initialized only by PRSTn: RTCSWComp
The following registers are initialized by PRSTn: RTCData, RTCMatch, RTCLoad, and
RTCCtrl.
30
14
29
13
0x8092_000C
0x8092_0000
0x8092_0004
0x8092_0008
0x8092_0010
0x8092_0098
Address
28
12
0x8092_0000 - Read Only
0x0000_0000
RTC Data Register. Contains the 32 bit RTC counter value. This counter is
incremented by the 1 Hz clock output from the RTC Trim module.
RTCDR:
27
11
Table 20-1. Real Time Clock Register Memory Map
26
10
"RTCSWComp"
Copyright 2007 Cirrus Logic
"RTCMatch"
"RTCLoad"
"RTCData"
"RTCCtrl"
"RTCSts"
25
Name
9
Counter value.
24
8
RTCDR
RTCDR
23
7
RTC Data Register
RTC Match Register
RTC Status/EOI Register
RTC Load Register
RTC Control Register
RTC Software Compensation
22
6
21
5
Description
20
4
19
3
18
2
17
1
DS785UM1
16
0
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