EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 54
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
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Manufacturer
Quantity
Price
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2
2-16
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2.3.5 Memory Map
The memory map for Synchronous Memory Boot and Asynchronous Memory Boot is shown
in
If internal Boot Mode is selected and the register BootModeClr has been written, the address
range 0x0000_0000 -> 0x0000_FFFF is occupied by the internal Boot ROM until the internal
Boot Code is completed. After boot completion, either Synchronous or Asynchronous
memory is re-mapped to occupy this address space.
NOTE: Some memory locations are listed as Reserved. These memory locations should not
be used. Reading from these memory locations will yield invalid data. Writing to these
memory locations may cause unpredictable results.
Table
2-7.
0xE000_0000 - 0xEFFF_FFFF
0xD000_0000 - 0xDFFF_FFFF
0xC000_0000 - 0xCFFF_FFFF
0xF000_0000 - 0xFFFF_FFFF
0x9000_0000 - 0xBFFF_FFFF
0x8080_0000 - 0x8FFF_FFFF
0x7000_0000 - 0x7FFF_FFFF
0x6000_0000 - 0x6FFF_FFFF
0x5000_0000 - 0x5FFF_FFFF
0x4000_0000 - 0x4FFF_FFFF
0x3000_0000 - 0x3FFF_FFFF
0x2000_0000 - 0x2FFF_FFFF
0x1000_0000 - 0x1FFF_FFFF
0x0001_0000 - 0x0FFF_FFFF
0x8010_0000 - 0x807F_FFFF
0x8000_0000 - 0x800F_FFFF
0x0000_0000 - 0x0000_FFFF
Register
11,12,14
Address Range
13
15
Reserved
FCSE PID Register: (Read/Write) ARM9TDMI core addresses ranging from 0 to 32MB are
translated by this register to A + FCSE*32MB and then sent to the MMU. If turned off,
straight addresses are sent to the MMU.
Test Register Only: Reads or writes will cause unpredictable behavior.
Table 2-7. Global Memory Map for the Two Boot Modes
Table 2-6. CP15 ARM920T Register Description (Continued)
Copyright 2007 Cirrus Logic
Sync memory (nSDCE2)
Sync memory (nSDCE1)
Sync memory (nSDCE0)
Sync memory (nSDCE3)
Sync memory (nSDCE3)
Sync Memory Boot
if INTBOOT is selected
Async memory (nCS0)
APB mapped registers
AHB mapped registers
Async memory (nCS7)
Async memory (nCS6)
Async memory (nCS3)
Async memory (nCS2)
Async memory (nCS1)
Internal Boot ROM
PCMCIA (Slot 0)
ASD0 Pin = 1
Reserved
Reserved
Not Used
or
Description
Async Memory Boot
Sync memory (nSDCE3)
Sync memory (nSDCE2)
Sync memory (nSDCE1)
Sync memory (nSDCE0)
if INTBOOT is selected
AHB mapped registers
Async memory (nCS7)
Async memory (nCS6)
Async memory (nCS3)
Async memory (nCS2)
Async memory (nCS1)
Async memory (nCS0)
Async memory (nCS0)
APB mapped registers
Internal Boot ROM
PCMCIA (Slot 0)
ASD0 Pin = 0
Not Used
Reserved
Reserved
or
DS785UM1
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