EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 39
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
DS785UM1
2.2.1 Features
2.1 Introduction
2.2 Overview: ARM920T Core
2ARM920T Core and Advanced High-Speed Bus (AHB)
This chapter describes the ARM920T Core and the Advanced High-Speed Bus (AHB).
The ARM920T is a Harvard architecture core with separate 16 kbyte instruction and data
caches with an 8-word line length. The ARM Core utilizes a five-stage pipeline consisting of
fetch, decode, execute, data memory access, and write stages.
Key features include:
• ARM V4T (32-bit) and Thumb (16-bit compressed) instruction sets
• 32-bit Advanced Micro-Controller Bus Architecture (AMBA)
• 16 kbyte Instruction Cache with lockdown
• 16 kbyte Data Cache (programmable write-through or write-back) with lockdown
• Write Buffer
• MMU for Microsoft Windows CE and Linux operating systems
• Translation Look-aside Buffers (TLB) with 64 Data and 64 Instruction Entries
• Programmable Page Sizes of 64 kbyte, 4 kbyte, and 1 kbyte
• Independent lockdown of TLB Entries
• JTAG Interface for Debug Control
• Co-processor Interface
Copyright 2007 Cirrus Logic
Chapter 2
2-1
2
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