EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 288
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 288 of 824
- Download datasheet (13Mb)
8
8-24
Graphics Accelerator
EP93xx User’s Guide
31
15
Default:
Mask:
Definition:
Bit Descriptions:
Address:
30
14
29
13
28
12
0x0000_0000
0x001F_001F
Destination Pixel Start/End register
RSVD:
EPEL:
SPEL:
BLKSRCSTRT
0x8004_0008 - Read/Write
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Destination Pixel Location - Read/Write
For the ending pixel (at the ending X-Y coordinate of the
1st scan line) of the destination image for a block copy, the
value in this field specifies where the beginning bit of the
ending pixel is located in a 32-bit word. For example, if the
beginning bit of an 8-bit pixel is located at bit 24 of a 32-bit
word, EPEL = 0x18.
The EPEL field and the ADR field in the
register together define the destination ending pixel’s
address in the SDRAM frame buffer. Granularity must be a
multiple of the pixel size in all video display modes. For
example,.acceptable values in 8 bpp mode are 0x00,
0x08, 0x10, and 0x18.
Source Pixel Location - Read/Write
For the starting pixel (at the starting X-Y coordinate of the
1st scan line) of the destination image for a block copy, the
value in this field specifies where the beginning bit of the
pixel is located in a 32-bit word. For example, if the
beginning bit of a 16-bit pixel is located at bit 16 of a 32-bit
word, PEL = 0x10.
The SPEL field and the ADR field in the
register together define the destination starting pixel’s
address in the SDRAM frame buffer. Granularity must be a
multiple of the pixel size in all video display modes. For
example,.acceptable values in 8 bpp mode are 0x00,
0x08, 0x10, and 0x18.
ADR
24
8
ADR
23
7
22
6
21
5
20
4
19
3
“BLKDESTSTRT”
“BLKDESTSTRT”
18
2
17
1
DS785UM1
NA
16
0
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