EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 7
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 9. 1/10/100 Mbps Ethernet LAN Controller ........................................... 9-1
DS785UM1
8.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.2 Descriptor Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13
9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-40
8.6.4 Block Copy Function......................................................................................................8-18
9.1.1 Detailed Description ........................................................................................................9-1
9.1.2 MAC Engine ....................................................................................................................9-3
9.1.3 Packet Transmission Process .........................................................................................9-5
9.1.4 Transmit Back-Off............................................................................................................9-7
9.2.1 Receive Descriptor Processor Queues .........................................................................9-13
9.2.2 Receive Descriptor Queue ............................................................................................9-13
9.2.3 Receive Status Queue...................................................................................................9-16
9.2.4 Interrupts .......................................................................................................................9-37
9.2.5 Initialization....................................................................................................................9-37
8.6.4.1 Example of Block Copy................................................................................8-21
9.1.1.1 Host Interface and Descriptor Processor .......................................................9-1
9.1.1.2 Reset and Initialization...................................................................................9-2
9.1.1.3 Power-down Modes .......................................................................................9-2
9.1.1.4 Address Space ..............................................................................................9-2
9.1.2.1 Data Encapsulation........................................................................................9-3
9.1.3.1 Carrier Deference ..........................................................................................9-5
9.1.4.1 Transmission .................................................................................................9-7
9.1.4.2 The FCS Field................................................................................................9-7
9.1.4.3 Bit Order ........................................................................................................9-8
9.1.4.4 Destination Address (DA) Filter .....................................................................9-8
9.1.4.5 Perfect Address Filtering ...............................................................................9-8
9.1.4.6 Hash Filter .....................................................................................................9-9
9.1.4.7 Flow Control.................................................................................................9-10
9.1.4.8 Receive Flow Control...................................................................................9-10
9.1.4.9 Transmit Flow Control..................................................................................9-10
9.1.4.10 Rx Missed and Tx Collision Counters ........................................................9-11
9.1.4.11 Accessing the MII ......................................................................................9-11
9.2.3.1 Receive Status Format ................................................................................9-18
9.2.3.2 Receive Flow ...............................................................................................9-21
9.2.3.3 Receive Errors .............................................................................................9-22
9.2.3.4 Receive Descriptor Data/Status Flow ..........................................................9-23
9.2.3.5 Receive Descriptor Example .......................................................................9-24
9.2.3.6 Receive Frame Pre-Processing...................................................................9-25
9.2.3.7 Transmit Descriptor Processor Queues.......................................................9-26
9.2.3.8 Transmit Descriptor Queue..........................................................................9-26
9.2.3.9 Transmit Descriptor Format .........................................................................9-28
9.2.3.10 Transmit Status Queue..............................................................................9-30
9.2.3.11 Transmit Status Format .............................................................................9-32
9.2.3.12 Transmit Flow ............................................................................................9-34
9.2.3.13 Transmit Errors ..........................................................................................9-35
9.2.3.14 Transmit Descriptor Data/Status Flow .......................................................9-36
9.2.4.1 Interrupt Processing.....................................................................................9-37
9.2.5.1 Interrupt Processing.....................................................................................9-38
9.2.5.2 Receive Queue Processing .........................................................................9-38
9.2.5.3 Transmit Queue Processing ........................................................................9-38
9.2.5.4 Other Processing .........................................................................................9-38
9.2.5.5 Transmit Restart Process ............................................................................9-39
©
Copyright 2007 Cirrus Logic, Inc.
EP93xx User’s Guide
vii
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