EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 176
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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6
VICxVectAddr
6-14
Vectored Interrupt Controller
EP93xx User’s Guide
31
15
Definition:
Bit Descriptions:
Address:
Definition:
Note: Reading from this register provides the address of the ISR, and indicates to the priority
Note: If you are using the VIC and a program/debugger ever reads address VIC_BASE + 0x30,
30
14
• The ISR reads the VICxVectAddr register when an IRQ interrupt is generated
• At the end of the ISR, the VICxVectAddr register is written with any value in order to
update the priority hardware.
hardware that the interrupt is being serviced. Writing to this register indicates to the
priority hardware that the interrupt has been serviced. The register should be used as
follows:
a value must be written to VIC_BASE + 0x30. If not, only higher priority interrupts are
enabled and there are no higher priority interrupts. Therefore, no more interrupts will
occur. If you use the VIC in Vectored Interrupt mode, this is not an issue.
29
13
28
12
Protection Enable Register. The VICxProtection register enables or disables
protected register access. If the bus master cannot generate accurate
protection information, leave this register in its reset state to allow User mode
access.
VIC1VectAddr: 0x800B_0030 - Read/Write
VIC2VectAddr: 0x800C_0030 - Read/Write
Vector Address Register. The VICxVectAddr register contains the Interrupt
Service Routine (ISR) address of the currently active interrupt.
Reading or writing to the register at other times can cause incorrect operation.
RSVD:
Protection:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Enables or disables protected register access. When
enabled, only Privileged mode accesses (reads and
writes) can access the interrupt controller registers. When
disabled, both User mode and Privileged mode can
access the registers. This bit is cleared to ‘0’ on reset, and
can only be accessed in Privileged mode.
24
VectorAddr
VectorAddr
8
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0
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