EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 466
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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11
HcFmNumber
HcPeriodicStart
11-26
Universal Serial Bus Host Controller
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Description:
Address:
RSVD
30
14
30
14
29
13
29
13
28
12
28
12
FRT:
0x8002_003C
0x0000_0000
Contains a 16-bit counter used as a timing reference between the host
controller and its driver.
RSVD:
FN:
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
FrameRemainingToggle. This bit is loaded from the
FrameIntervalToggle field of HcFmInterval whenever
FrameRemaining reaches 0. This bit is used by HCD for
the synchronization between FrameInterval and
FrameRemaining.
Reserved. Unknown During Read.
FrameNumber. This is incremented when
HcFmRemaining is re-loaded. It will be rolled over to 0x0
after 0xFFFF. When entering the USBOPERATIONAL
state, this will be incremented automatically. The content
will be written to HCCA after HC has incremented the
FrameNumber at each frame boundary and sent a SOF
but before HC reads the first ED in that Frame. After
writing to HCCA, HC will set the StartofFrame in
HcInterruptStatus.
24
24
8
8
RSVD
RSVD
FN
23
23
7
7
PS
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0
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