EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 261

• Manufacturer Part Number: EP9301-IQZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-IQZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 24
• Mounting Type: Surface Mount
• Operating Temperature Min: -40°C
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1250

VSigStrtStop
DS785UM1
31
15
Address: 0x8003_0208
Default: 0x0000_0000
Definition: Vertical Signature Bounds Start/Stop register
30
14
RSVD
RSVD
29
13
28
12
CLKEN:
BLANK:
HSYNC:
VSYNC:
PEN:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Clock Enable - Read/Write
Writing a ‘1’ to this bit enables the CLKEN control for
calculation in the video signature.
Writing a ‘0’ to this bit disables the CLKEN control for
calculation in the video signature.
Blank - Read/Write
Writing a ‘1’ to this bit enables the BLANK output for
calculation in the video signature.
Writing a ‘0’ to this bit disables the BLANK output for
calculation in the video signature.
Horizontal Synchronization - Read/Write
Writing a ‘1’ to this bit enables the HSYNC output for
calculation in the video signature.
Writing a ‘0’ to this bit disables the HSYNC output for
calculation in the video signature.
Vertical Synchronization - Read/Write
Writing a ‘1’ to this bit enables the VSYNC output for
calculation in the video signature.
Writing a ‘0’ to this bit disables the VSYNC output for
calculation in the video signature.
Pixel Bits Enable - Read/Write
Writing ‘1’s to these bits enables respective pixel bits for
calculation in the video signature.
Writing ‘0’s to these bits disables respective pixel bits for
calculation in the video signature.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
22
6
STOP
STRT
21
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
7-79
0
7