EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 415
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
DS785UM1
10.2.2 Internal M2P/P2M Channel Register Map
The DMA Memory Map above includes the base address mapping for the channel registers
for each of the 10 M2P/P2M channels that are shown in the following table, the Internal
M2P/P2M Channel Register Map. This mapping is common for each channel thus offset
addresses from the bases in
Channel Base Address + 0x000C
Channel Base Address + 0x001C
Channel Base Address + 0x002C
Channel Base Address + 0x003C
0x8000_03C4 -> 0x8000_FFFC
Channel Base Address + 0x0000
Channel Base Address + 0x0004
Channel Base Address + 0x0008
Channel Base Address + 0x0010
Channel Base Address + 0x0014
Channel Base Address + 0x0018
Channel Base Address + 0x0020
Channel Base Address + 0x0024
Channel Base Address + 0x0028
Channel Base Address + 0x0030
Channel Base Address + 0x0034
Channel Base Address + 0x0038
0x8000_0340 -> 0x8000_037C
ARM920T Address
0x8000_03C0
0x8000_0380
Offset
Note:See
Note:* - write this location once to clear the interrupt (see Interrupt register description
Table 10-4. Internal M2P/P2M Channel Register Map
for which bits this rule applies to).
Table 10-3
Table 10-3
Table 10-3. DMA Memory Map
Copyright 2007 Cirrus Logic
M2P Channel 8 Registers (Tx)
“INTERRUPT”
“CURRENTx”
“CURRENTx”
DMA Global Interrupt register
“CONTROL”
“MAXCNTx”
“MAXCNTx”
“PPALLOC”
Register
“REMAIN”
“STATUS”
Reserved
Reserved
Reserved
Reserved
Reserved
DMA Channel Arbitration
“BASEx”
“BASEx”
Name
for Channel Base Addresses
Description
Not Used
register
are shown in
R/W TC *
Access
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Table
Bits
16
16
32
32
16
32
32
6
3
4
8
Channel Base Address
10-4.
(see register description)
Channel dependant
0x8000_03C4
0x8000_0340
Reset Value
0
0
0
0
0
0
0
0
0
0
EP93xx User’s Guide
DMA Controller
10-21
10
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